The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device making use of a charge coupled device (hereinafter abbreviated as CCD).
Recently, a one-dimensional image sensor making use of silicon has come into practical use. A two-dimensional device is also coming into practical use in place of the vidicon type imaging tube in the prior art. However, there still remain a few shortcomings in such a solid-state image sensor. An image lag, as will be described below, is one of the shortcomings of the solid-state image sensor.
The problem of image lag in the solid-state image sensor is especially liable to arise in an interline system CCD sensor. Generally, among the solid-state image sensors, an image sensor making use of a CCD has a low noise because of its small output capacitance. Hence, it can achieve imaging under a low illuminance. However, in the interline system CCD sensor, the proportion of the intensity of imaging lag relative to the original image intensity is increased as illuminance is lowered. This increased lag image intensity deteriorates the quality of the reproduced picture. Accordingly, the limit of usable low illuminance is determined not by a noise but by the effect of the image lag. Thus, if the image lag is reduced, the lower limit of usable illuminance can be widely extended to thereby enable imaging at lower light levels.
Now the mechanism which causes a generation of the image lag will be explained.
The solid-state imaging device in the prior art includes a plurality of N.sup.+ -type photo-sensitive regions in a P-type silicon substrate. The N.sup.+ -type photo-sensitive regions are formed in at least one column. In a two-dimensional image sensor, they are formed in a plurality of columns. The imaging device also includes CCD charge transfer sections parallel with the respective columns. The charge transfer between the CCD charge transfer sections and the corresponding columns of photo-sensitive regions is controlled by applying given potentials to gate electrodes provided therebetween.
It should be noted that the N.sup.+ -type photo-sensitive regions forms a well of a potential by a built-in-potential of the PN-junction between that region and the P-type silicon substrate. Thus, the electric charge produced by incident light to the N.sup.+ -type photo-sensitive region is accumulated in this potential well. In response to an application of a potential to the gate electrode, the electric charge accumulated in this potential well is transferred to the CCD charge transfer section. During this transfer process, the transfer of the electric charge is initially effected quickly because the charge accumulated in the potential well is so great that the potential well is held at a sufficiently low potential, as compared to the potential at the point below the gate electrode. Eventually, however, the potential at the potential well gradually approaches the potential under the gate electrode. Hence, the speed of transfer of electric charge is gradually slowed. As a result, during a predetermined period when a given potential is applied to the gate electrode, the electric charge accumulated in the N.sup.+ -type photo-sensitive region cannot be completely transferred to the CCD charge transfer section. Therefore, a part of the accumulated electric charge remains in the N.sup.+ -type photo-sensitive region. This residual electric charge is read out when a given potential is subsequently applied to the gate electrode. As a result, an image lag appears in the reproduced picture image.